Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and other types of logic blocks, such as memories, microprocessors, digital signal processors (DSPs), and the like. The CLBs, IOBs, and other logic blocks are interconnected by a programmable interconnect structure. The CLBs, IOBs, logic blocks, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, logic blocks, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as digital clock managers (DCMs), input/output (I/O) transceivers, boundary scan logic, and the like.
A growing problem with FPGAs, as well as with ICs in general, is that the available number of transistors to implement functionality is outpacing the number of input/output (IO) pins available to handle the input and output data. Consequently, FPGAs (and other ICs) are becoming IO bound. In the particular application of inter-FPGA (or inter-IC) communication, such IO limitations can deleteriously affect the bandwidth of the inter-communication of data between the devices.
Accordingly, there exists a need in the art for a method and apparatus for inter-IC communication with improved bandwidth.